The present invention relates to a method of fabricating a semiconductor device having a trench interconnection structure.
With a tendency toward higher integration of semiconductor devices, a dimensional rule of inner interconnections becomes finer, and thereby line widths of inner interconnections and spaces therebetween become narrower. However, to guarantee a reliability of interconnections, especially, a resistance against electromigration, cross-sections of interconnections must be ensured, with a result that thicknesses of interconnection layers cannot be thinned so much. As a result, an aspect ratio (ratio of height/width) of each of an interconnection portion and a space portion becomes higher. For this reason, a related art interconnection process comes to require a technique for processing interconnections finer and thicker than conventional ones and also to require a technique for burying narrower and deeper spaces with insulating films.
With respect to the former technique, however, since multi-layerization of Al based interconnections is progressed, it becomes difficult to process the Al alloy based interconnections into rectangular shapes. Also, with respect to Cu based interconnections expected to be preferentially used in the future from the viewpoints of improvement in reliability of interconnection and reduction in resistance of interconnection, there are various problems in terms of a technique of processing Cu based interconnections, and consequently, it seems that a Cu based interconnection is very difficult to be formed as an interconnection with a high aspect ratio.
Besides, the latter technique has been realized using a bias ECR (Electron Cyclotron Resonance)-CVD process or a SOG (Spin On Glass) etch-back process; however, the above process is complicated, to cause problems that a fabrication cost is increased and a treatment time is made longer. Further, to realize global perfect planarization, it is additionally required to form a dummy interconnection or to polish an insulating film by a CMP (Chemical Mechanical Polish) process, with a result that the process is further complicated.
To solve these problems together, attention has been recently focused on a trench interconnection process shown in FIGS. 6A to 6D. In this process, a patterned resist layer 61 is formed on an insulating film 60 containing an etching stopper layer 60a (FIG. 6A). A trench 62 for forming a trench interconnection is formed by etching the insulating film 60 using the resist layer 61 as an etching mask, and then the resist layer 61 is removed (FIG. 6B). A barrier metal layer 63 is formed over the entire surface of the insulating film 60 and an interconnection material 64 is formed to bury the trench 62 therewith (FIG. 6C). The interconnection material 64 is removed by CMP or the like except for part of the interconnection material 64 buried in the trench 62, to form a trench interconnection 65 (FIG. 6D).
The use of such a trench interconnection process is expected to solve the various problems accompanied by the above-described tendency toward finer-geometries. This is because if an insulating film is planarized by CMP once, it is possible to eliminate planarization of an interlayer insulating film formed thereafter, as a general rule; it is also possible to eliminate burying a narrow space with an interlayer insulating film; and further, it is possible to eliminate fine processing (lithography and etching) for an interconnection material. The use of the trench interconnection process having the above advantages, however, further requires development of the process techniques shown in the following terms (1) to (3):
(1) a technique for forming a fine trench in an insulating film; PA1 (2) a technique for burying a trench with an interconnection material to form a trench interconnection; and PA1 (3) a technique for removing an interconnection material deposited on portions other than a trench. PA1 (4) a technique for forming a narrow and deep (aspect ratio: high) connection hole and a trench; and PA1 (5) a technique for simultaneously burying a narrow and deep (aspect ratio: high) connection hole and a trench with an interconnection material. PA1 (A) A lower trench interconnection 100 is formed, and an interlayer insulating film 102 having on its surface an etching stopper layer 101 is formed. A connection hole 103 is formed in the interlayer insulating film 102; an adhesive layer 104 is formed in the connection hole 103, and a W plug 105 is formed in the connection hole 103 (FIG. 10A). PA1 (B) An additional insulating film 106 is further formed, and a trench 107 for forming an upper interconnection is formed (FIG. 10B). PA1 (C) A backing film 108 is formed in the trench 106, and the trench 106 is buried with an interconnection material, to form an upper trench interconnection 109 (FIG. 10C). PA1 a substrate; PA1 an interlayer insulating film formed on the substrate; PA1 a connection hole formed in the interlayer insulating film; PA1 a connection plug formed by burying the connection hole with a connection hole burying material; PA1 a trench formed in the interlayer insulating film; and PA1 a trench interconnection formed by burying the trench with an interconnection material; PA1 wherein the connection plug enters in the trench interconnection in such a manner that at least part of a side surface of sid connection plug is brought in contact with the trench interconnection. PA1 a step (a) of forming an insulating film on a substrate; PA1 a step (b) of forming a connection hole in the insulating film; PA1 a step (c) of burying the connection hole with a connection hole burying material to form a connection plug; PA1 a step (d) of forming a trench in the insulating film; and PA1 a step (e) of burying the trench with an interconnection material to form a trench interconnection; PA1 wherein the formation of the trench in the step (d) is performed in such a manner that at least part of a side wall of the connection plug buried in the connection hole is exposed in the trench. PA1 a step (A) of forming a first insulating film on a substrate; PA1 a step (B) of forming a connection hole in the insulating film; PA1 a step (C) of burying the connection hole with a connection hole burying material to form a connection plug; PA1 a step (D) of additionally forming a second insulating film on the first insulating film; PA1 a step (E) of forming a trench in the second insulating film and the first insulating film; and PA1 a step (F) of burying the trench with an interconnection material to form a trench interconnection; PA1 wherein the formation of the trench at the step (E) is performed in such a manner that at least part of a side wall of the connection plug buried in the connection hole at the step (D) is exposed in the trench.
With respect to the technique shown in (1), a process of forming a fine trench in an insulating film can is very easier than a process of forming a fine interconnection from a layer of an interconnection material. With respect to the techniques shown in (2) and (3), for either an Al interconnection or a Cu interconnection, an attempt has been made to combine a reflow process or a high pressure reflow process with the CMP process; or to combine the CVD process with the CMP process. Here, the reflow process is carried out by forming a film of an interconnection material such as an Al alloy, heating the film at a temperature in a range of a re-crystallization temperature to a melting point of the material to soften the material thereby increasing a fluidity of the material, and making the material reflow in a trench or a connection hole previously formed with a barrier metal (TiN/Ti) layer, thereby burying the trench or connection hole with the interconnection material. The high pressure reflow process is carried out by heating an interconnection material in a high pressure inert gas atmosphere, thereby making the interconnection material reflow in a trench or a connection hole previously formed with a barrier metal layer (which process is similar to a hot extrusion process).
In particular, from the viewpoints of workability of Cu and/or use of an organic based low dielectric constant material as an insulating material, the trench interconnection process, which is out of fine processing of an interconnection material itself and planarization of the buried insulating film, has a large merit, and therefore, the trench interconnection process is expected to be preferentially used in the future.
Further, there is known a duel damascene interconnection technique which is developed from the above-described trench interconnection process. This technique will be described with reference to FIGS. 7A to 7C. First, both a connection hole (contact hole or via-hole) 71 and a trench 72 are formed in an interlayer insulating film 70 containing an etching stopper layer 70a (FIG. 7A). Then, a barrier metal layer 73 is formed over the entire surface of the interlayer insulating film 70, and the connection hole 71 and the trench 72 are simultaneously buried with an interconnection material 74 (FIG. 7B). Next, the interconnection material 74 is removed by CMP except for part of the interconnection material 74 buried in the trench 72, to form a connection plug 75 and a trench interconnection 76 at a time (FIG. 7C). If such a dual damascene interconnection technique can be applied to a mass-production process of semiconductor devices, it is possible to form both a connection hole and an interconnection pattern at a time, and hence to significantly reduce the process cost and shorten the treatment time. To be applied to a mass-production process of semiconductor devices, however, this technique is required to mainly solve subjects shown in the following terms (4) and (5):
In particular, with respect to the subject (5), a related art reflow process is insufficient, and an ability of burying a trench with an interconnection material must be further enhanced. Further, even in the case of the CVD process having a high burying ability, the CVD technique itself for depositing Al and Cu is required to be further enhanced. To be more specific, at present, the duel damascene process cannot be applied to fabrication of semiconductor devices, unless in the case of the Al-CVD, problems such as surface coarsening, film formation rate, resistivity, and doping of an impurity are solved, and in the case of the Cu-CVD, in addition to the above problems, various problems regarding a CVD system such as re-depositi on of Cu, cleaning, and generation of dust are solved.
Accordingly, in the case of development of a trench interconnection process, an attempt has been made to practically use a related art trench interconnection process in combination of a CVD-W (tungsten) plug technique known to be excellent in burying ability rather than application of the duel damascene process.
Incidentally, with a tendency toward a finer dimensional rule of interconnections, areas of fine connection holes at lithography and etching steps become one of factors of restricting a reduction in area of the total cell. Further, in consideration of a misalignment at the lithography step, according to a related art structure, as shown in FIG. 8, a margin 83 of typically about 0.1 .mu.m is given to an interconnection pattern 82 at a connection hole 81 portion. As a result, there arises a problem that it is difficult to reduce a pitch of interconnections.
In recent years, a so-called borderless connection hole-interconnection structure is being examined, in which a misalignment margin is omitted from an interconnection pattern. With this structure, as shown in FIG. 9, a pitch of interconnections can be further reduced correspondingly to elimination of such a misalignment margin. Such a structure is expected to become an important technique in the future, particularly, for interconnections low in current density in cell, although there is a problem in terms of a reliability (degradation of a resistance against electromigration upon occurrence of a misalignment, or the like).
Accordingly, such a borderless connection hole-interconnection structure should be realized for a trench interconnection process using the CVD-W plug technique.
Incidentally, the trench interconnection process combined with the CVD-W plug technique generally used as a connection hole burying process is generally carried out in accordance with a process sequence shown in FIGS. 10A to
In the trench interconnection process using such a CVD-W plug technique, however, if a borderless connection hole-interconnection structure is adopted without provision of a misalignment margin for the upper trench interconnection, there arises the following problem:
That is, as shown in FIG. 11A, in the case of a misalignment of a connection hole 103 to a lower trench interconnection 100, since the connection hole 103 is formed in such a manner as to be engraved along a side surface of the lower trench 100 by over-etching, a contact area between the lower trench 100 and a W plug 105 os not significantly reduced, so that a contact resistance therebetween is not significantly increased. On the other hand, as shown in FIG. 11B, a misalignment of an upper trench interconnection 109 to the connection hole 103 directly exerts an effect on a reduction in contact area therebetween, thereby seriously increasing a contact resistance therebetween.